For an analog-to-digital converter (hereinafter referred to as an ADC) built in a CMOS semiconductor circuit, use is heavily made of an analog voltage level comparator, that is, a so-called chopper comparator circuit. FIG. 2-1 shows a configuration of a conventional chopper comparator circuit. Further, FIG. 2-2 shows the configuration thereof in detail. Herein, there is described the configuration thereof, having two inverter circuitries, however, there can be a case of the configuration having three inverter circuitries.
A chopper comparator circuit 10 has an input terminal 11 for receiving an analog input voltage Vin, and an input terminal 13 for receiving a reference voltage Vref. The input terminal 11 is connected to a node N11 via a first switch SW11 made up of an analog switch. The input terminal 13 is connected to the node N11 via a second switch SW13 made up of an analog switch. A first capacitor C11 extends between the node N11 and a node N13. The node N13 is connected to a node N15 via a first CMOS inverter 15 that is a first inverter circuitry, and also via a-third switch SW15 made up of an analog switch. As shown in FIG. 2-2, the first CMOS inverter 15 comprises a p-channel MOS transistor (hereinafter referred to as a PMOS transistor) T11 and an n-channel MOS transistor (hereinafter referred to as an NMOS transistor) T13. The PMOS transistor T11 has a gate connected to the node 13 via a node N21, a source connected to the plus side of a power source Vdd, and a drain connected to a node N15 via a node N23. The NMOS transistor T13 has a gate connected to the node 13 via the node N21, a drain connected to the node N15 via the node N23, and a source connected to the ground. A second capacitor C13 extends between the node N15 and a node N17. The node N17 is connected to a node N19 via a second CMOS inverter 17 that is a second inverter circuitry, and also via a fourth switch SW17 made up of an analog switch. As shown in FIG. 2-2, the second CMOS inverter 17 comprises a PMOS transistor T15 and an NMOS transistor T17. The PMOS transistor T15 has a gate connected to the node 17, a source connected to the plus side of the power source Vdd, and a drain connected to the node N19. The NMOS transistor T17 has a gate connected to the node 17, a drain connected to the node N19, and a source connected to the ground. The node N19 is connected to an output terminal 19 for outputting an output voltage Vout.
The chopper comparator circuit 10 makes use of the first and second CMOS inverters 15, 17 as an amplifier, respectively, while joining the first CMOS inverter 15 with the second CMOS inverter 17 through the intermediary of the second capacitor C13, thereby executing various operations such as offset compensation, comparison, sample hold, and so forth.
The chopper comparator circuit 10 described above normally operates as follows.
First, the first to fourth switches, SW11 to SW17, are caused to operate based on a clock signal (not shown). At the outset, the first, third, and fourth switches, SW11, SW15, and SW17, are turned into the closed (on) condition while the second switch SW13 is turned into the open (off) condition, whereupon a voltage at the node 11 will be Vin, a voltage at the node N13 will be the threshold voltage Vth1 of the first CMOS inverter 15, a voltage at the node N15 will be at the same value as that for the node N13 (that is, Vth1), a voltage at the node N17 will be the threshold voltage Vth2 of the second CMOS inverter 17, and a voltage at the node N19 will be at the same value as that for the node N17 (that is, Vth2) to be thereby sent out from the output terminal 19 as the output voltage Vout.
At this point in time, charge Q1 of the first capacitor C11 is expressed by the following formula (1), and charge Q2 of the second capacitor C13 is expressed by the following formula (2):Q1=C1(Vin−Vth1)  (1)Q2=C2(Vth1−Vth2)  (2)where capacitance of the first capacitor C11 is C1 and capacitance of the second capacitor C13 is C2.
Thus, the first capacitor C11 retains a potential difference between the input voltage Vin and the threshold voltage Vth1 of the first CMOS inverter 15 while the second capacitor C13 retains a potential difference in offset voltage between the first CMOS inverter 15 and the second CMOS inverter 17 (that is, a potential difference between the threshold voltage Vth1 of the first CMOS inverter 15 and the threshold voltage Vth2 of the second CMOS inverter 17).
Subsequently, the first to fourth switches SW11 to SW17 are caused to operate based on a clock signal (not shown). At this point in time, the first, third, and fourth switches, SW11, SW15, and SW17, are turned into the “off” condition while the second switch SW13 is turned into the “on” condition, whereupon a voltage at the node 11 will be Vref, and voltages at the respective nodes, N13, N15, N17, N19, undergo a change. As a result, the chopper comparator circuit 10 sends out the output voltage Vout at a value worked out in the following manner from the output terminal 19.
Assuming that a voltage at the node N13 at this point in time is Vx1, charge Q1′ of the first capacitor C11 is expressed by the following formula (3):Q1′=C1(Vref−Vx1)  (3)In this case, Q1=Q1′ Accordingly, based on the formulas (1) and (3), Vx1 is expressed by the following formula (4):Vx1=Vref−Vin+Vth1  (4)
Further, assuming that a gain of the first CMOS inverter 15 is A1, a voltage V15 at the node N15 is expressed by the following formula (5-1), and based on the formula (4), formula (5-2) is substituted for the formula (5-1) as follows:V15=A1(Vx1−Vth1)+Vth1  (5-1)V15=A1(Vref−Vin,)+Vth1  (5-2)
Still further, assuming that a voltage at the node N17 is Vx2, charge Q2′ of the second capacitor C13 is expressed by the following formula (6):Q2′=C2(V15−Vx2)  (6)Herein, Q2=Q2′ Accordingly, based on the formulas (2), (6), and (5-2), Vx2 is expressed by the following formula (7):Vx2=A1(Vref−Vin)+Vth2  (7)Further, assuming that a gain of the second CMOS inverter 17 is A2, the output voltage Vout from the node N19 is expressed by the following formula (8-1), and based on the formula (7), formula (8-2) is substituted for the formula (8-1) as follows:Vout=A2(Vx2−Vth2)+Vth2  (8-1)Vout=A1A2(Vref−Vin)+Vth2  (8-2)
Thus, the chopper comparator circuit 10 sends out the output voltage Vout at a value worked out based on the formula (8-2) from the output terminal 19.
Hence, with the chopper comparator circuit 10, the first CMOS inverter 15 and the second CMOS inverter 17 are caused to operate as an amplifier having a gain of A1, A2, thereby amplifying a potential difference (Vref−Vin) between the input voltage Vin and the reference voltage Vref. Thus, the chopper comparator circuit 10 executes comparison operation.
The chopper comparator circuit 10 as described above has been disclosed in, for example, JP, 1998-65502, A (Patent Document 1).
(Patent Document 1) JP, 1998-65502, A (FIG. 9)
With the conventional chopper comparator circuit, since the gain thereof used to be set high, power consumption has increased, so that there has been the need for cutting down on power consumption.
More specifically, because there is, for example, a case where the ADC is put to applications requiring high resolving power, a gain (in other word, the gain of the CMOS inverters 15, 17, respectively) of the chopper comparator circuit 10 is set high in order to enable the ADC to obtain a high gain.
In order that the gain of the CMOS inverters 15, 17, respectively, is set high, however, the transistors T11 through T17, making up the CMOS inverters 15, 17, respectively, need to be enlarged in size. Enlargement in the size of the respective transistors T11 through T17 will result in an increase in the power consumption of the chopper comparator circuit 10. Consequently, there has been the need for cutting down on the power consumption of the chopper comparator circuit 10 of the conventional type.